View ADN8834_8355942.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ultra c ompact, 1.5 a thermoelectric cooler (tec) controller data sheet ADN8834 features patented high efficiency single inductor architecture inte grated low r dson mos fets for the tec controller tec voltage and current operation monitoring no external sense resistor required independent tec he ating and cooling current limit settings programmable maximum tec voltage 2.0 mhz pwm dr iver switching frequency external synchronization two inte grated, zero drift, rail - to - rail chop per am plifiers capable of ntc or rtd thermal sensors 2.5 0 v reference output with 1% accuracy te mperature lock indicator available in a 25 - ball, 2.5 mm 2.5 mm wlcsp or in a 24- lead, 4 mm 4 mm lfcsp applications tec temperature control o ptical modules optical fiber amplifiers optical networking systems instruments requiring tec temperature control functional block dia gram tec current and vo lt age sense and limit controller linear power st age tec driver pwm power st age oscill a t or volt age reference out1 vlim/ sd vtec ilim pvin itec en/s y vref ldr sfb in2 p in2n in1 p in1n out2 sw pgndx vdd agnd error am p com p am p 12954-001 figure 1 . general description the ADN8834 is a monolithic tec controller with an integrated tec controller . it has a linear power stage, a pulse - width modulation ( pwm ) power stage, and two zero - drift , rail - to - rail operational amplifiers. the l inear controller works with the pwm driver to control t he internal power mosfets in an h- bridge configuration . by measuring the thermal sensor feedback voltage and using the integr ated operational amplifiers as a proportional integral differential (pid) compensator to condition the signal , the ADN8834 drives current through a tec to settle the temperature of a laser diode or a passive component attached to the tec module to the programmed target temperature . the ADN8834 supports negative temperature coefficient (ntc) thermistors as well as positive temperature c oefficient (ptc) resistive temperature detectors (rtd). the target temperature is set as an analog voltage input either from a digital - to - analog converter (dac) or from an external resistor divider. the temperature control loop of the ADN8834 is stabilized by pid compensation uti lizing the built in , zero drift chopper amplifiers. the internal 2.50 v reference voltage provides a 1% accurate output that is used to bias a thermistor temperature sensing bridge as well as a voltage divider network to program the maximum tec current and voltage limits for both the heating and cooling modes. with the zero drift chop per amplifiers, extremely good long - term temperature stability is maintained via an autonomous analog temperature control loop. table 1. tec family models device no. mosfet thermal loop package adn8831 discrete digital/a nalog lfcsp (cp -32-7) adn8833 integrated digital wlcsp (cb -25-7) , lfcsp (cp -24-15 ) ADN8834 integrated digital/analog wlcsp (cb -25-7) , lfcsp (cp -24-15 ) rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by imp lication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2015 analog devices, inc. all rights reserved. technical support www.analog.com
ADN8834 data sheet rev. a | page 2 of 27 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ............................................. 8 detailed functional block diagram ............................................ 12 theory of operation ...................................................................... 13 analog pid control ................................................................... 14 digital pid control .................................................................... 14 powering the controller ............................................................ 14 enable and shutdown ................................................................ 15 oscillator clock frequency ....................................................... 15 temperature lock indicator (lfcsp only) ........................... 15 soft start on power-up .............................................................. 15 tec voltage/current monitor ................................................. 16 maximum tec voltage limit .................................................. 16 maximum tec current limit ................................................. 17 applications information .............................................................. 18 signal flow .................................................................................. 18 thermistor setup ........................................................................ 18 thermistor amplifier (chopper 1) .......................................... 19 pid compensation amplifier (chopper 2) ............................ 19 mosfet driver amplifiers ...................................................... 20 pwm output filter requirements .......................................... 20 input capacitor selection .......................................................... 21 power dissipation....................................................................... 21 pcb layout guidelines .................................................................. 23 block diagrams and signal flow ............................................. 23 guidelines for reducing noise and minimizing power loss ..... 23 example pcb layout using two layers ................................. 24 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history 8/15rev. 0 to rev. a added 24-lead lfcsp ....................................................... universal changes to features section and table 1 ...................................... 1 changes to table 2 ............................................................................ 3 changes to table 3 ............................................................................ 6 added figure 3; renumbered sequentially .................................. 7 changes to figure 13 ........................................................................ 9 changes to figure 23 and figure 24 ............................................. 11 changes to figure 25 ...................................................................... 12 changes to powering the controller section and figure 27 caption ............................................................................................. 14 change to soft start on power-up section ................................. 15 change to figure 33 ....................................................................... 18 changes to table 7 .......................................................................... 21 added table 8; renumbered sequentially .................................. 21 updated outline dimensions ....................................................... 27 changes to ordering guide .......................................................... 27 4/15revision 0: initial version
data sheet ADN8834 specifications v in = 2.7 v to 5.5 v, t j = ? 40 c to + 125 c for minimum/maximum specifications, and t a = 25 c for typical specifications, unless otherwise noted. table 2. parameter symbol test conditions /comments min typ max unit power supply driver supply voltage v pvin 2.7 5.5 v controller supply voltage v vdd 2.7 5.5 v supply current i vdd pwm not switching 3.3 5 ma shutdown current i sd en/sy = agnd or vlim/sd = agnd 350 700 a undervoltage lockout (uvlo) v uvlo v vdd rising 2.45 2.55 2.65 v uvlo hysteresis uvlo hyst 80 90 100 mv reference voltage v vref i vref = 0 ma to 10 ma 2.475 2.50 2.525 v linear output output voltage v ldr i ldr = 0 a low 0 v high v pvin v maximum source current i ldr_source t j = ? 40 c to + 105 c 1.5 a t j = ?40 c to + 125 c 1.2 a maximum sink current i ldr_sink t j = ? 40 c to + 105 c 1.5 a t j = ? 40 c to + 125 c 1.2 a on resistance i ldr = 0.6 a p - mosfet r ds_pl(on) wlcsp, v pvin = 5.0 v 35 50 m? wlcsp, v pvin = 3.3 v 44 60 m? lfcsp, v pvin = 5.0 v 50 65 m? lfcsp, v pvin = 3.3 v 55 75 m? n - mosfet r ds_nl(on) wlcsp, v pvin = 5.0 v 31 50 m? wlcsp, v pvin = 3.3 v 40 55 m? lfcsp, v pvin = 5.0 v 45 70 m? lfcsp, v pvin = 3.3 v 50 80 m? leakage current p - mosfet i ldr_p_lkg 0.1 10 a n - mosfet i ldr_n_lkg 0.1 10 a linear amplifier gain a ldr 40 v/v ldr short - circuit threshold i ldr_sh_gndl ldr short to pgndl, enter hiccup 2.2 a i ldr_sh_pvin(l) ldr short to pvin, enter hiccup ?2.2 a hiccup cycle t hiccup 15 ms pwm output output voltage v sfb i sfb = 0 a v low 0.06 v pvin v high 0.93 v pvin v maximum source current i sw_source t j = ?40c to +105c 1.5 a t j = ?40c to +125c 1.2 a maximum sink current i sw_sink t j = ?40c to +105c 1.5 a t j = ?40c to +125c 1.2 a on resistance i sw = 0.6 a p - mosfet r ds_ps(on) wlcsp, v pvin = 5.0 v 47 65 m? wlcsp, v pvin = 3.3 v 60 80 m? lfcsp, v pvin = 5.0 v 60 80 m? lfcsp, v pvin = 3.3 v 70 95 m? rev. a | page 3 of 27
ADN8834 data sheet parameter symbol test conditions /comments min typ max unit n - mosfet r ds_ns(on) wlcsp, v pvin = 5.0 v 40 60 m? wlcsp, v pvin = 3.3 v 45 65 m? lfcsp, v pvin = 5.0 v 45 75 m? lfcsp, v pvin = 3.3 v 55 85 m? leakage current p - mosfet i sw_p_lkg 0.1 10 a n - mosfet i sw_n_lkg 0.1 10 a sw node rise time 1 t sw_r c sw = 1 nf 1 ns pwm duty cycle 2 d sw 6 93 % sfb input bias current i sfb 1 2 a pwm oscillator internal oscillator frequency f osc en/sy high 1.85 2.0 2.15 mhz en/sy input voltage low v en/sy_ilow 0.8 v high v en/sy_ihigh 2.1 v external synchronization frequency f sync 1.85 3.25 mhz synchronization pulse duty cycle d sync 10 90 % en/ sy rising to pwm rising delay t sync_pwm 50 ns en/ sy to pwm lock time t sy_lock number of sync cycles 10 cycles en/sy input current i en/sy 0.3 0.5 a pull - down current 0.3 0.5 a error/compensation amplifiers input offset voltage v os1 v cm1 = 1.5 v, v os1 = v in1p ? v in1 n 10 100 v v os2 v cm2 = 1.5 v, v os2 = v in2p ? v in2 n 10 100 v input voltage range v cm1 , v cm2 0 v vdd v common - mode rejection ratio (cmrr) cmrr 1 , cmrr 2 v cm1 , v cm2 = 0.2 v to v vdd ? 0.2 v 120 db output voltage high v oh1 , v oh2 v vdd ? 0.04 v low v ol1 , v ol2 10 mv power supply rejection ratio (psrr) psrr 1 , psrr 2 120 db output current i out1 , i out2 sourcing and sinking 5 ma gain bandwidth product 1 gbw 1 , gbw 2 v out1 ,v out2 = 0.5 v to v vdd ? 1 v 2 mhz tec current limit ilim input voltage range cooling v ilimc 1.3 v vref ? 0.2 v heating v ilimh 0.2 1.2 v current - limit threshold cooling v ilimc_th v itec = 0.5 v 1.98 2.0 2.02 v heating v ilimh_th v itec = 2 v 0.48 0.5 0.52 v ilim input current heating i ilimh ?0.2 +0.2 a cooling i ilimc sourcing current 37.5 40 42.5 a cooling to heating current detection threshold i cool_heat_th 40 ma tec voltage limit voltage limit gain a vlim (v drl ? v sfb )/v vlim 2 v/v vlim/sd input voltage range 1 v vlim 0.2 v vdd /2 v vlim/sd input current cooling i ilimc v out2 < v vref /2 ?0.2 +0.2 a heating i ilimh v out2 > v vref /2, sinking current 8 10 12.2 a rev. a | page 4 of 27
data sheet ADN8834 parameter symbol test conditions /comments min typ max unit tec current measurement (wlcsp) current sense gain r cs v pvin = 3.3 v 0.525 v/a v pvin = 5 v 0.535 v/a current measurement accuracy i ldr _error 700 ma i ldr 1.5 a, v pvin = 3.3 v ? 10 + 10 % 800 ma i ldr 1.5 a, v pvin = 5 v ? 10 +10 % itec voltage accuracy v itec _@ _7 00_ ma v pvin = 3.3 v , cooling, v vref /2 + i ldr r cs 1.597 1.618 1.649 v v itec _@ _ ? 7 00_ma v pvin = 3.3 v , heating, v vref /2 ? i ldr r cs 0.846 0.883 0.891 v v itec _@ _8 00_ ma v pvin = 5 v, cooling, v vref /2 + i ldr r cs 1.657 1.678 1.718 v v itec _@ _ ? 8 00_ma v pvin = 5 v, heating, v vref /2 ? i ldr r cs 0.783 0.822 0.836 v tec current measurement (lfcsp) current sense gain r cs v pvin = 3.3 v 0.525 v/a v pvin = 5 v 0.525 v/a current measurement accuracy i ldr_error 700 ma i ldr 1 a, v pvin = 3.3 v ?1 5 +15 % 800 ma i ldr 1 a, v pvin = 5 v ? 15 +15 % itec voltage accuracy v itec_@_700_ma v pvin = 3.3 v, cooling, v vref /2 + i ldr r cs 1.374 1.618 1.861 v v itec_@_?700_ma v pvin = 3.3 v, heating, v vref /2 ? i ldr r cs 0.750 0.883 1.015 v v itec_@_800_ma v pvin = 5 v, cooling, v vref /2 + i ldr r cs 1.419 1.678 1.921 v v itec_@_?800_ma v pvin = 5 v, heating, v vref /2 ? i ldr r cs 0.705 0.830 0.955 v itec voltage output range v itec i tec = 0 a 0 v vref ? 0.05 v itec bias voltage v itec i ldr = 0 a 1.210 1.250 1.285 v maximum itec output current i itec ?2 +2 ma tec voltage measurement voltage sense gain a vtec 0.24 0.25 0.26 v/v voltage measurement accuracy v vtec _@ _1 _v v ldr C v sfb = 1 v, v vref/2 + a vtec (v ldr C v sfb ) 1.475 1.50 1.525 v vtec output voltage range v vtec 0.005 2.625 v vtec bias voltage v vtec_b v ldr = v sfb 1.225 1.250 1.285 v maximum vtec output current r vtec ?2 +2 ma temperature good (lfcsp o nly) tmpgd low output voltage v tmpgd_lo no load 0.4 v tmpgd high output voltage v tmpgd_ho no load 2.0 v tmpgd output low impedance r tmpg d _low 25 ? tmpgd output high impedance r tmpg d _low 50 ? high threshold v out1_thh in2n tied to out2, v in2p = 1.5 v 1.54 1.56 v low threshold v out1_thl in2n tied to out2, v in2p = 1.5 v 1.40 1.46 v internal soft start soft start time t ss 150 ms vlim/sd shutdown vlim/sd low voltage threshold v vlim/ sd_thl 0.07 v thermal shutdown thermal shutdown threshold t shdn_th 170 c thermal shutdown hysteresis t shdn_hys 17 c 1 this specification is guaranteed by design. 2 this specification is guaranteed by characterization. rev. a | page 5 of 27
ADN8834 data sheet absolute maximum rat ings table 3. parameter rating pvin to pgndl (wlcsp) ? 0.3 v to +5.75 v pvin to pgnds (wlcsp) ? 0.3 v to +5.75 v pvinl to pgndl (lfcsp) ? 0.3 v to +5.75 v pvins to pgnds (lfcsp) ? 0.3 v to +5.75 v ldr to pgndl (wlcsp) ? 0.3 v to v pvin ldr to pgndl (lfcsp) ? 0.3 v to v pvinl sw to pgnds ? 0.3 v to +5.75 v sfb to agnd ? 0.3 v to v vdd agnd to pgndl ? 0.3 v to +0.3 v agnd to pgnds ? 0.3 v to +0.3 v vlim/sd to agnd ? 0.3 v to v vdd ilim to agnd ? 0.3 v to v vdd vref to agnd ?0.3 v to +3 v vdd to agnd ? 0.3 v to +5.75 v in1p to agnd ? 0.3 v to v vdd in1 n to agnd ? 0.3 v to v vdd out1 to agnd ?0.3 v to +5.75 v in2p to agnd ? 0.3 v to v vdd in2 n to agnd ? 0.3 v to v vdd out2 to agnd ?0.3 v to +5.75 v en/sy to agnd ? 0.3 v to v vdd itec to agnd ?0.3 v to +5.75 v vtec to agnd ?0.3 v to +5.75 v maximum current vref to agnd 20 ma out1 to agnd 50 ma out2 to agnd 50 ma itec to agnd 50 ma vtec to agnd 50 ma junction temperature 125c storage temperature range ?65c to +150c lead temperature (soldering, 10 sec) 260c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extende d periods may affect product reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages, and i s based on a 4 - layer standard jedec board. table 4. package type ja jc unit 25- ball wlcsp 48 0.6 c/w 24- lead lfcsp 37 1.65 c /w esd caution rev. a | page 6 of 27
data sheet ADN8834 rev. a | page 7 of 27 pin configurations and function descriptions a b c d e 12345 vlim/ sd ilim vref vdd in2p in1p out2 agnd in2n en/sy out1 ADN8834 top view (balls on the bottom side) in1n itec vtec sfb sw ldr pgndl pvin pgnds pgnds sw pvin pgndl ldr 2.54mm 2.54mm 0.5mm pitch 12954-002 figure 2. wlcsp pin configuration (top view) 12954-200 2 1 3 4 5 6 1 8 1 7 1 6 1 5 1 4 1 3 v r e f v d d i l i m v l i m / s d o u t 2 i n 2 n p g n d s s w p v i n s p v i n l l d r p g n d l 8 9 1 0 1 1 7 e n / s y v t e c s f b i t e c 1 2 p g n d s a g n d 2 0 1 9 2 1 t m p g d p g n d l o u t 1 2 2 i n 1 n 2 3 i n 1 p 2 4 i n 2 p ADN8834 top view (not to scale) notes 1. exposed pad. solder to the analog ground plane on the board. figure 3. lfcsp pin configuration (top view) table 5. pin function descriptions pin no. mnemonic description wlcsp lfcsp a1, a2 18, 19 pgndl power ground of the linear tec controller. n/a 1 20 tmpgd temperature good output. a3 21 out1 output of the error amplifier. a4 23 in1p noninverting input of the error amplifier. a5 24 in2p noninverting input of the compensation amplifier. b1, b2 17 ldr output of the linear tec controller. b3 22 in1n inverting input of the error amplifier. b4 1 in2n inverting input of the compensation amplifier. b5 3 vlim/sd voltage limit/shutdown. this pin sets the cooling and heating tec voltage limits. when this pin is pulled low, the device shuts down. c1, c2 n/a 1 pvin power input for the tec controller. n/a 1 16 pvinl power input for the linear tec driver. n/a 1 15 pvins power input for the pwm tec driver. c3 11 itec tec current output. c4 2 out2 output of the compensation amplifier. c5 4 ilim current limit. this pin sets th e tec cooling and heating current limits. d1, d2 14 sw switch node output of the pwm tec controller. d3 9 vtec tec voltage output. d4 8 en/sy enable/synchronization. set this pin high to en able the device. an external synchronization clock input can be applied to this pin. d5 5 vdd power for the controller circuits. e1, e2 12, 13 pgnds power ground of the pwm tec controller. e3 10 sfb feedback of the pwm tec controller output. e4 7 agnd signal ground. e5 6 vref 2.5 v reference output. n/a 1 0 epad exposed pad. solder to th e analog ground plane on the board. 1 n/a means not applicable.
ADN8834 data sheet t ypical p erformance c haracteristics t a = 25c, unless otherwise noted. 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1.0 1.5 efficienc y (%) tec current (a) v in = 3.3v v in = 5v 12954-003 figure 4 . efficiency vs. tec current at v in = 3.3 v and 5 v in cooling mode with 2 ? load 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1.0 1.5 efficienc y (%) tec current (a) v in = 3.3v v in = 5v 12954-004 figure 5 . efficiency vs. tec current at v in = 3.3 v and 5 v in heating mode with 2 load 0 10 20 30 40 50 60 70 80 90 100 effciency(%) load = 2 load = 3 load = 4 load = 5 12954-105 0 0.5 1.0 1.5 tec current (a) figure 6 . efficiency vs. tec current at v in = 3.3 v with different load s in cooling mode 0 10 20 30 40 50 60 70 80 90 100 0 1.5 efficienc y (%) tec current (a) load = 2 load = 3 load = 4 load = 5 12954-106 0.5 1.0 figure 7 . efficiency vs. tec current at v in = 3.3 v with different load s in heating mode 2.7 5.0 4.5 4.0 3.5 3.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 maximum tec current (a) input vo lt age a t pvin (v) load = 2 load = 3 load = 4 load = 5 12954-107 5.5 figure 8 . maximum tec current vs. input voltage at pvin (v in = 3.3 v) , without voltage and current limit in cooling mode 2.7 5.5 5.0 4.5 4.0 3.5 3.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 maximum tec current (a) input vo lt age a t pvin (v) load = 2 load = 3 load = 4 load = 5 12954-108 figure 9 . maximum tec current vs. input voltage at pvin (v in = 3.3 v) , without voltage and current limit in heating mode rev. a | page 8 of 27
data sheet ADN8834 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 0 20 40 60 80 100 120 140 160 180 200 tempout [v out1 ] vo lt age error (%) time (seconds) t = 15c t = 25c t = 35c t = 45c t = 55c 12954-109 figure 10 . thermal stability over ambient temperature at v in = 3.3 v, v tempset = 1 v ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 0 20 40 60 80 100 120 140 160 180 200 tempout [v out1 ] vo lt age error (%) time (seconds) t = 15c t = 25c t = 35c t = 45c t = 55c 12954- 1 10 figure 11 . thermal stability over ambient temperature at v in = 3.3 v, v tempset = 1.5 v v in = 2.7v a t no load v in = 3.3v a t no load v in = 5.5v a t no load v in = 2.7v a t 5m a load v in = 3.3v a t 5m a load v in = 5.5v a t 5m a load 1.0 ?50 0 50 ambient temper a ture (c) 100 150 0.8 0.6 0.4 0.2 0 v ref error (%) ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 12954- 11 1 figure 1 2 . v ref error vs. ambient temperature 0.20 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0 10 9 8 7 6 5 4 3 2 1 v ref (%) load current at v ref (ma) 12954-201 v in = 3.3v, itec = 0a v in = 3.3v, itec = 0.5a, cooling v in = 3.3v, itec = 0.5a, heating v in = 5.0v, itec = 0a v in = 5.0v, itec = 0.5a, cooling v in = 5.0v, itec = 0.5a, heating figure 13 . v ref load regulation ?20 ?15 ?10 ?5 0 5 10 15 20 0 0.5 1.0 1.5 itec current reading error (%) tec current (a) v in = 3.3v v in = 5v 12954-010 figure 14 . itec current reading error vs. tec current in cooling mode ?20 ?15 ?10 ?5 0 5 10 15 20 ? 1.5 ?1.0 ?0.5 0 itec current reading error (%) tec current (a) v in = 3.3v v in = 5v 12954-013 figure 15. itec current reading error vs. tec current in heating mode rev. a | page 9 of 27
ADN8834 data sheet rev. a | page 10 of 27 ?20 ?15 ?10 ?5 0 5 10 15 20 0.5 1.0 1.5 2.0 2.5 vtec voltage reading error (%) tec voltage (v) v in = 3.3v v in = 5v 12954-011 figure 16. vtec voltage reading error vs. tec voltage in cooling mode ? 20 ?15 ?10 ?5 0 5 10 15 20 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 vtec voltage reading error (%) tec voltage (v) v in = 3.3v v in = 5v 12954-014 figure 17. vtec voltage reading error vs. tec voltage in heating mode figure 18. cooling to heating transition figure 19. zero crossing tec current zoom in from heating to cooling figure 20. zero crossing tec current zoom in from cooling to heating figure 21. typical enable waveforms in cooling mode, v in = 3.3 v, load = 2 , tec current = 1 a 4 1 ch1 500mv ch2 500mv m10ms a ch4 ?8ma t 5.4ms b w b w ch3 300ma ? b w 12954-120 pwm (tec?) tec current ldo (tec+) 4 1 ch1 500mv ch2 500mv m10ms a ch4 12ma t 5.4ms b w b w ch3 200ma ? b w pwm (tec?) tec current ldo (tec+) 12954-120 ch1 500mv ch2 500mv m200ms a ch4 ?108ma t ?28.000ms b w b w ch4 200ma ? b w 4 1 pwm (tec?) tec current ldo (tec+) 12954-118 en tec current ldo (tec?) pwm (tec+) 12954-121 ch1 1v ch2 1v m20.0ms a ch3 800mv t 40ms b w b w ch3 2v b w ch4 500ma ? b w 3 4 1
data sheet ADN8834 rev. a | page 11 of 27 figure 22. typical enable waveforms in heating mode, v in = 3.3 v, load = 2 , tec current = 1 a figure 23. typical switch and voltage ripple waveforms in cooling mode v in = 3.3 v, load = 2 , tec current = 1 a figure 24. typical switch and voltage ripple waveforms in heating mode, v in = 3.3 v, load = 2 , tec current = 1 a 12954-122 3 4 2 en tec current ldo (tec+) pwm (tec?) ch1 1v ch2 1v m20.0ms a ch3 800mv t 40ms b w b w ch3 2v b w ch4 500ma ? b w 12954-202 3 1 2 sw ldo (tec+) pwm (tec?) ch1 20mv b w ch2 20mv b w m400ns a 2.50gs/s ch3 1.00v t 0.0s ch3 2.0v b w 12954-203 3 1 2 sw ldo (tec+) pwm (tec?) ch1 20mv b w ch2 20mv b w m400ns a 2.50gs/s ch3 1.00v t 0.0s ch3 2.0v b w
ADN8834 data sheet d et ailed functional block di agram v b linear amplifier v c 20k itec 1.25v 1.25v 1.25v 5k vtec 20k 20k 5k sfb in2p in2n out2 in1p in1n out1 1.25v vlim/sd v c v b = 2.5v a t vdd > 4.0v v b = 1.5v a t vdd < 4.0v band gap volt age reference v b vref 2.5v vdd agnd tec vo lt age limit and internal soft s t art compens a tion amplifier temper a ture error amplifier vdd ADN8834 vdd 40a 10a heating tec current sense ldr tec volt age sense sw pgnds pvin pwm power st age pwm mosfet driver en/sy sfb 20k 20k 20k 20k 100k v b v b 400k 80k pwm modul a t or pwm error amplifier ilim cooling itec 20 k tec current limit pgnds ldr pgndl pvin pgndl he a ting cooling clk shutdown 0.07v oscillator clk shutdown deglitch v high 2.1v v low 0.8v 2k 80k tec driver linear power st age + ? + ? 12954-018 figure 25 . detailed functional block diagram of the ADN8834 for the wlcsp rev. a | page 12 of 27
data sheet ADN8834 theory of operation the ADN8834 is a single chip tec controller that sets and stabilizes a tec temperature. a voltage applied to the input of the ADN8834 corresponds to the temperature setpoint of the target object attached to the tec . the ADN8834 controls an internal fet h - bridge whereby the direction of the current fed through the tec can be either positive (for cooling mode) , to pump heat away from the object attached to the tec , or negative (for heating mode) , to pump heat into the object attac hed to the tec. t emperature is measured with a thermal sensor attached to the target object and the sensed temperature (voltage) is fed back to the ADN8834 to complete a closed thermal control loop of the tec. for the best overall stability, couple the thermal sensor close to the tec . in most laser diode modules, a tec and a ntc thermistor are already mounted in the same package to regulate the laser diode temperature. the tec is differentially driven in an h - bridge configuration. the ADN8834 drives its internal mosfet transistors to provid e the tec current. t o provide good power efficiency and zero crossing quality , only one side of the h - bridge uses a pwm driver. only one inductor and one capacitor are required to filter out the switching frequency. the other side of the h - bridge uses a linear output without requiring any additional circuitry. this pro - prietary con figuration allows the ADN8834 to provide efficiency of >90%. f or most applications, a 1 h inductor, a 10 f capacitor, and a switching frequency of 2 mhz maintain less than 1% of the worst - case output voltage ripple across a tec. the maximum voltage across the tec and the current flowing through the tec are set by using the vlim/sd and ilim pins. the maximum cooling and heating currents can be set indepen - dently to allow asymmetric heating and cooling limits. for a dditional details , see the maximum tec voltage limit section and the maximum tec current limit section. ADN8834 l = 1h v in 2.7v t o 5.5v tec sw sfb ldr pgnds pvin vdd ilim vlim/sd itec tec volt age limit shutdown vtec + ? en/s y c sw_out 10f c l_out 0.1f c in 10f c vdd 0.1f r bp r fb pgnd l ntc tec volt age tec current enable/ sync tem p set in1n in1 p in2 p vref agnd out1 in2n out2 r c2 r c1 r v2 r v1 tec current limits c vref 0.1f r a r r b r i r d c d c f c i r p r x r th thermister 12954-019 figure 26 . typical application circuit with analog pid c ompensation in a t emperature c ontrol loop rev. a | page 13 of 27
ADN8834 data sheet analog pid control the ADN8834 integrates two self - correcting, auto - zero ing amplifiers ( chopper 1 and chopper 2 ). the chopper 1 a mplifier takes a thermal sensor input and converts or regulates the input to a linear voltage output. the out1 voltage is proportional to the object temperature. the out1 voltage is fed into the compensatio n amplifier ( chopper 2 ) and is compared with a temperature setpoint voltage, which creates an error voltage that is proportional to the difference. for autonomous analog temperature control, chopper 2 can be us ed to implement a pid network as shown in fi gure 27 to set the overall stability and response of the thermal loop. adjusting the pid network optimizes the step response of the tec control loop. a compromised settling time and the maximum current ringing becom e available when this adjustment is done. t o adjust the compensation network , see the pid compensation amplifier (chopper 2) section. digital pid control the ADN8834 can also be configured for use in a software controlled pi d loop. in this scenario , the chopper 1 amplifier can either be left unused or configured as a thermistor input amplifier connected to an external temperature measurement analog - to - digital converter ( adc ) . f or more information , see the thermistor amplifier ( chopper 1 ) section . if chopper 1 is left unused , tie in1 n and in1p to agnd. the chopper 2 amp lifier is used as a buffer for the external dac , whi ch controls the temperature set point. connect the dac to in2p and short t he in2 n and out2 pins together. see figure 27 for an ov erview of how to configure the ADN8834 external circuitry for digital pid control. powering the c ontroller the ADN8834 operates at an input voltage range of 2.7 v to 5.5 v that is applied to the vdd pin and the pvin pin for the wlcsp ( the pvins pin and pvinl pin for the lfcsp . the vdd pin is the input power for the driver and internal reference. the pvin input power pins are combined for both the linear and the switching d river. apply the same input voltage to all power input pins: vdd and pvin. in some circumstances, an rc l ow - pass filter can be adde d optionally between the pvin for the wlcsp (pvins and pvinl for the lfcsp ) and vdd pins to prevent high frequency noise from entering vdd, as sho wn in fi gure 27 . the capacitor and resistor values are typically 10 ? and 100 nf, respectively. when configuring power supply to the ADN8834 , keep in mind that at high current loads , the input voltage may drop substantially due to a voltage drop on the wires between the front - end power supply and the pvin for the wlcsp (pvins a nd pvinl for the lfcsp ) pin. leave a proper voltage margin when designing the front - end power supply to maintain the performance. minimize the trace length from the power supply to the pvin for the wlcsp (pvins and pvinl for the lfcsp ) p in to help mitigate the voltage drop. ADN8834 l = 1h v in 2.7v t o 5.5v tec sw sfb ldr pgnds pvin vdd ilim vlim/sd itec in2 p vtec tec volt age limit 2.5v vref + ? en/s y c sw_out 10f f sw = 2mhz c l_out 0.1f c in 10f c vdd 0.1f pgnd l enable in1n in1 p vref agnd in2n out2 out1 r v1 r v2 r c1 r c2 cooling and he a ting tec current limits c vref 0.1uf r a r 2.5v vref tec vo lt age readback tec current readback temper a ture set r b r fb r bp r x ntc thermister r th temper a ture readback adc dac 2.5v vref 2.5v vref 12954-020 fi gure 27 . tec c ontroller in a d igital t emperature c ontrol l oop (wlcsp) rev. a | page 14 of 27
data sheet ADN8834 rev. a | page 15 of 27 enable and shutdown to enable the ADN8834 , apply a logic high voltage to the en/sy pin while the voltage at the vlim/sd pin is above the maximum shutdown threshold of 0.07 v. if either the en/sy pin voltage is set to logic low or the vlim/sd voltage is below 0.07 v, the controller goes into an ultralow current state. the current drawn in shutdown mode is 350 a typically. most of the current is consumed by the vref circuit block, which is always on even when the device is disabled or shut down. the device can also be enabled when an external synchronization clock signal is applied to the en/sy pin, and the voltage at vlim/sd input is above 0.07 v. table 6 shows the combinations of the two input signals that are required to enable the ADN8834 . table 6. enable pin combinations en/sy input vlim/sd input controller >2.1 v >0.07 v enabled switching between high >2.1 v and low < 0.8 v >0.07 v enabled <0.8 v no effect 1 shutdown floating no effect 1 shutdown no effect 1 0.07 v shutdown 1 no effect means this signal has no effect in shutting down or in enabling the device. oscillator clock frequency the ADN8834 has an internal oscillator that generates a 2.0 mhz switching frequency for the pwm output stage. this oscillator is active when the enabled voltage at the en/sy pin is set to a logic level higher than 2.1 v and the vlim/sd pin voltage is greater than the shutdown threshold of 0.07 v. external clock operation the pwm switching frequency of the ADN8834 can be synchronized to an external clock from 1.85 mhz to 3.25 mhz, applied to the en/sy input pin as shown on figure 28. external clock source ADN8834 agnd en/sy 12954-021 figure 28. synchronize to an external clock connecting multiple ADN8834 devices multiple ADN8834 devices can be driven from a single master clock signal by connecting the external clock source to the en/sy pin of each slave device. the input ripple can be greatly reduced by operating the ADN8834 devices 180 out of phase from each other by placing an inverter at one of the en/sy pins, as shown in figure 29. ADN8834 ADN8834 external clock source agnd en/sy agnd en/sy 12954-022 figure 29. multiple ADN8834 devices driven from a master clock temperature lock indicator (lfcsp only) the tmpgd outputs logic high when the temperature error amplifier output voltage, v out1 , reaches the in2p temperature setpoint (tempset) voltage. the tmpgd has a detection range between 1.46 v and 1.54 v of v out1 and hysteresis. the tmpgd function allows direct interfacing either to the microcontrollers or to the supervisory circuitry. soft start on power-up the ADN8834 has an internal soft start circuit that generates aramp with a typical 150 ms profile to minimize inrush current during power-up. the settling time and the final voltage across the tec depends on the tec voltage required by the control voltage of voltage loop. the higher the tec voltage is, the longer it requires to be built up. when the ADN8834 is first powered up, the linear side discharges the output of any prebias voltage. as soon as the prebias is eliminated, the soft start cycle begins. during the soft start cycle, both the pwm and linear outputs track the internal soft start ramp until they reach midscale, where the control voltage, v c , is equal to the bias voltage, v b . from the midscale voltage, the pwm and linear outputs are then controlled by v c and diverge from each other until the required differential voltage is developed across the tec or the differential voltage reaches the voltage limit. the voltage developed across the tec depends on the control point at that moment in time. figure 30 shows an example of the soft start in cooling mode. note that, as both the ldr and sfb voltages increase with the soft start ramp and
ADN8834 data sheet rev. a | page 16 of 27 approach v b , the ramp slows down to avoid possible current overshoot at the point where the tec voltage starts to build up. v b ld r sfb time discharge prebias soft start begins tec voltage builds up reach voltage limit 12954-023 figure 30. soft start profile in cooling mode tec voltage/current monitor the tec real-time voltage and current are detectable at vtec and itec, respectively. voltage monitor vtec is an analog voltage output pin with a voltage proportional to the actual voltage across the tec. a center vtec voltage of 1.25 v corresponds to 0 v across the tec. convert the voltage at vtec and the voltage across the tec using the following equation: v vtec = 1.25 v + 0.25 (v ldr ? v sfb ) current monitor itec is an analog voltage output pin with a voltage proportional to the actual current through the tec. a center itec voltage of 1.25 v corresponds to 0 a through the tec. convert the voltage at itec and the current through the tec using the following equations: v itec_cooling = 1.25 v + i ldr r cs where the current sense gain ( r cs ) is 0.525 v/a. v itec_heating = 1.25 v ? i ldr r cs maximum tec voltage limit the maximum tec voltage is set by applying a voltage divider at the vlim/sd pin to protect the tec. the voltage limiter operates bidirectionally and allows the cooling limit to be different from the heating limit. using a resistor divider to set the tec voltage limit separate voltage limits are set using a resistor divider. the internal current sink circuitry connected to vlim/sd draws a current when the ADN8834 drives the tec in a heating direction, which lowers the voltage at vlim/sd. the current sink is not active when the tec is driven in a cooling direction; therefore, the tec heating voltage limit is always lower than the cooling voltage limit. vlim/sd tec voltage limit and internal soft start 10a heating clk disable v ref r v1 r v2 12954-024 sw open = v vlimc sw closed = v vlimh figure 31. using a resistor divider to set the tec voltage limit calculate the cooling and heating limits using the following equations: v vlim_cooling = v ref r v2 /( r v1 + r v2 ) where v ref = 2.5 v. v vlim_heating = v vlim_cooling ? i sink_vlim r v1 ||r v2 where i sink_vlim = 10 a. v tec_max_cooling = v vlim_cooling a vlim where a vlim = 2 v/v. v tec_max_heating = v vlim_heating a vlim
data sheet ADN8834 rev. a | page 17 of 27 maximum tec current limit to protect the tec, separate maximum tec current limits in cooling and heating directions are set by applying a voltage combination at the ilim pin. using a resistor divider to set the tec current limit the internal current sink circuitry connected to ilim draws a 40 a current when the ADN8834 drives the tec in a cooling direction, which allows a high cooling current. use the following equations to calculate the maximum tec currents: v ilim_heating = v ref r c2 /( r c1 + r c2 ) where v ref = 2.5 v. v ilim_cooling = v ilim_heating + i sink_ilim r c1 ||r c2 where i sink_ilim = 40 a. cs cooling ilim cooling max tec r v i v25.1 _ __ ? ? where r cs = 0.525 v/a. cs heating ilim heating max tec r v i _ __ v25.1 ? ? v ilim_heating must not exceed 1.2 v and v ilim_cooling must be more than 1.3 v to leave proper margins between the heating and the cooling modes. vdd 40a ilim cooling itec + ? tec current limit v ref r c1 r c2 sw open = v ilimh sw closed = v ilimc 12954-025 figure 32. using a resistor divi der to set the tec current limit
ADN8834 data sheet applications informa tion linear amplifier ldr tec current sense sw pgnds pvin pwm power s t age pwm mosfet driver control sfb pwm modul a t or pgnds ldr tec pgndl pvin pgndl + ? oscillator in2p out2 in2n tec driver linear power s t age + ? + ? in1p out1 in1n z 2 z 1 r fb r r x r th v ref /2 v ref v tempset v out2 v out1 v in v in temper a ture error amplifier a v = r fb /(r th + r x ) ? r fb /r chopper 1 pid compens a tion amplifier a v = z 2 /z 1 chopper 2 12954-026 figure 33 . signal flow block diagram signal flow the ADN8834 integrates two auto - zero amplifiers , defined as the chopper 1 amplifier and the chopper 2 amplifier. both of the amplifiers can be used as standalone amplifiers ; therefore, the implementation of temperature control can vary. figure 33 shows the signal flow through the ADN8834 , and a typical implementation of the temperature control loop using the chopper 1 ampli fier and the chopper 2 amplifier. in figure 33 , the chopper 1 and chopper 2 amplifiers are config - ured as the thermistor input amplifier and the pid compensation amplifier, respectively. the thermistor input amplifier gains the t hermistor voltage, then outputs to the pid compensation amplifier. t he pid compensation amplifier then compensates a loop res ponse ove r the frequency domain. the output from the compensation loop at out2 is fed to the linear mosfet gate driver. the voltage at ldr is fed with o ut2 into the pwm mosfet gate driver. including the internal transistors, the gain of the differential o utput section is fixed at 5 . for details on the output drivers, see the mosfet driver amplifier section. thermistor setup the thermistor has a nonlinear relationship to temperature; near optimal linearity over a specified temperature range can be achieved with the proper value of r x pla ced in series with the thermisto r. first, the resistance of the thermis tor must be known, where ? r low = r th at t low ? r mid = r th at t mid ? r high = r th at t high t low and t high are the endpoints of the temperature range and t mid is the average. in some cases, with only the constant available , calculate r th using the following equation: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = r r th t t r r 1 1 exp r th is a resistance at t ( k ) . r r is a resistance at t r ( k ) . rev. a | page 18 of 27
data sheet ADN8834 rev. a | page 19 of 27 calculate r x using the following equation: ? ? ? ? ? ? ? ? ?? ? ? ? mid high low high low high mid mid low x rrr rrrrrr r 2 2 thermistor amplifier (chopper 1) the chopper 1 amplifier can be used as a thermistor input amplifier. in figure 33, the output voltage is a function of the thermistor temperature. the voltage at out1 is expressed as: 2 1 ref fb x th fb out1 v r r rr r v ? ? ? ? ? ? ? ? ? ?? ? ? where: r th is a thermistor. r x is a compensation resistor. calculate r using the following equation: r = r x + r th_@_25c v out1 is centered around v ref /2 at 25c. an average temperature- to-voltage coefficient is ?25 mv/c at a range of 5c to 45c. ?15 5 25 45 0 2.5 65 0.5 1.0 1.5 2.0 temperature (c) v out1 (v) 12954-027 figure 34. v out1 vs. temperature pid compensation amplifier (chopper 2) use the chopper 2 amplifier as the pid compensation amplifier. the voltage at out1 feeds into the pid compensation amplifier. the frequency response of the pid compensation amplifier is dictated by the compensation network. apply the temperature set voltage at in2p. in figure 39, the voltage at out2 is calculated using the following equation: ) ( tempset out1 tempset out2 vv z1 z2 vv ? ? ? where: v tempset is the control voltage input to the in2p pin. z1 is the combination of r i , r d , and c d (see figure 35). z2 is the combination of r p , c i , and c f (see figure 35). the user sets the exact compensation network. this network varies from a simple integrator to proportional-integral (pi), pid (proportional-integral-derivative), or any other type of network. the user also determines the type of compensation and component values because they are dependent on the thermal response of the object and the tec. one method to empirically determine these values is to input a step function to in2p; thus changing the target temperature, and adjust the compensation network to minimize the settling time of the tec temperature. a typical compensation network for temperature control of a laser module is a pid loop consisting of a very low frequency pole and two separate zeros at higher frequencies. figure 35 shows a simple network for implementing pid compensation. to reduce the noise sensitivity of the control loop, an additional pole is added at a higher frequency than that of the zeros. the bode plot of the magnitude is shown in figure 36. use the following equation to calculate the unity-gain crossover frequency of the feed-forward amplifier: tecgai n r r rr r cr f fb x th fb ii 0db ? ? ? ? ? ? ? ? ? ? ? ?? 2 1 to ensure stability, the unity-gain crossover frequency must be lower than the thermal time constant of the tec and thermistor. however, this thermal time constant is sometimes unspecified, making it difficult to characterize. there are many texts written on loop stabilization, and it is beyond the scope of this data sheet to discuss all methods and trade-offs for optimizing compensation networks. v out1 is a convenient measure to gauge the thermal instability of the system, which is also known as tempout. if the thermal loop is in steady state, the tempout voltage equals the tempset voltage, meaning that the temperature of the controlled object equals the target temperature. out1 in2n out2 pid compensator chopper 2 in2p ADN8834 v tempset r i r d c d c f c i r p 12954-028 figure 35. implementing a pid compensation loop frequency (hz log scale) magnitude (log scale) 0db 1 2 r i c i r p r i 1 2 r i c d 1 2 r p c i 1 2 c d (r d +r i ) r p r d || r i 12954-029 figure 36. bode plot for pid compensation
ADN8834 data sheet mosfet driver amplif ier s the ADN8834 has two separate mosfet drivers: a switched output or pulse - width modulated (pwm) amplifier, and a high gain linear amplifier. each amplifier h as a pair of outputs that drive the g ates of the internal mosfets, which, in turn, drive the te c as shown in figure 33. a voltage across the tec is mo nitored via the sfb and ldr pins . although both mosfet drivers achieve the same result, to provide constant voltage and high current, their operation is different . the exact equations for the two outputs are v l dr = v b ? 40( v out2 ? 1.25 v) v sfb = v ldr + 5( v out2 ? 1.25 v) where: v out2 is the voltage at out2. v b is determined by v vdd as v b = 1.5 v for v vdd < 4.0 v v b = 2.5 v for v vdd > 4.0 v the compensation network that receives the temperature set voltage and the thermistor voltage fed by the input amplifier determines the voltage at out2 . v l dr and v sfb have a low limit of 0 v and an upper limit of v vdd . figure 37, figure 38 , and figure 39 show the graphs of these equations. out2 (v) ldr (v) 1.25 0.75 0.25 0 1.75 2.25 2.75 ?2.5 2.5 7.5 0 5.0 v sys = 5.0v v sys = 3.3v 12954-030 figure 37 . l dr voltage vs. out2 voltage 12954-031 sfb (v) out2 (v) 1.25 0.75 0.25 0 1.75 2.25 2.75 ?2.5 2.5 7.5 0 5.0 v sys = 5.0v v sys = 3.3v figure 38 . sfb voltage vs. out2 voltage ?2.5 ?5.0 0 2.5 5.0 out2 (v) v sys = 5.0v v sys = 3.3v vtec (v) ldr ? sfb 1.25 0.75 0.25 0 1.75 2.25 2.75 12954-032 figure 39 . tec voltage vs. out2 voltage pwm o utput f ilter r equirements a type three compensator internally compensates the pwm amplifi er. as the poles and zeros of the compensator are designed a nd fixed by assuming the resonance frequency of the output lc tank being 50 khz, the selection of the inductor and the capacitor must follow this guideline to ensure system stability. inductor selection the inductor selection determines the inductor current ripple and loop dynamic response. larger inductance results in smaller current ripple and slower transient response as smaller inductanc e r esults in the opposite performance. to optimize the performance , the trade - of f must be made between transient response speed, efficiency, and component size. calculate t he inductor value with the following equation: ( ) l sw in out sw in out sw i f v v v v l ? = _ _ C w here: v sw_out is the pwm amplifier output. f sw is the switching frequency (2 mhz by default). ?i l is the inductor current ripple. a 1 h inductor is typically recommended to allow reasonable output capacitor selection while maintain ing a low inductor current ripple. if lower inductance is required , a minimum inductor v alue of 0.68 h is suggested to ensure that the current ripple is set to a value between 30% and 40% of the maximum load current, which is 1.5 a. except for the inductor value, the equivalent dc resistance (dcr) inherent in the metal conductor is also a cr itical factor for inductor selection. the dcr accounts for most of the power loss on the inductor by dcr i out 2 . using an inductor with high dcr degrades the overall efficiency significantly. in addition, there is a conduct voltage drop across the inductor because of the dcr. when the pwm amplifier is sinking current in cooling mode, this voltage drive s the minimum voltage of the amplifier higher than 0.06 v in by at least tenth of millivolts. similarly, the maxim um pwm amplifier output voltage is lower than 0.93 v in . rev. a | page 20 of 27
data sheet ADN8834 this voltage drop is proportional to the value of the dcr and it reduce s the output voltage range at the tec. when selecting an inductor, en sure that the saturation current rating is higher than th e maximum current peak to prevent sat - uration. in general, ceramic multilayer inductors are suitable for low c urrent application s due to small size and low dcr . when the noise level is critical, use a shielded ferrite inductor to reduce the electromagnetic interference ( emi ) . table 7. recommended inductor s vendor value device no. footprint toko 1.0 h 20%, 2.6 a ( t yp ical ) dfe201612r -h - 1r0m 2.0 1.6 taiyo yuden 1.0 h 20%, 2.2 a (typical) makk2016t1r0m 2.0 1.6 murata 1.0 h 20%, 2.3 a ( t yp ical ) l qm2mpn1r0mgh 2.0 1.6 capacitor selection the output capacitor selection determines the output voltage ripple, transient response, as well as the loop dynamic response of the pwm amplifier output. use the following equation to select t he capacitor: ( ) out sw in out sw in out sw v f l v v v v c ? = 2 _ _ ) ( 8 C note that the voltage caused by the product of current ripple , i l , and the capacitor e quivalent s eries r esistance (esr) also add up to the total output voltage ripple. selecting a capacitor with low esr can increase overall regulation and efficiency performance. table 8. recommended capacitors vendor value device no. footprint (mm) murata 10 f 1 0%, 10 v zrb18ad71a106ke01l 1.6 0.8 murata 10 f 2 0%, 10 v grm188d71a106ma73 1.6 0.8 taiyo yuden 10 f 2 0%, 10 v lmk107bc6106ma - t 1.6 0.8 input capacitor sele ction on the p vin pin, the amplifiers require an input capacitor to decouple the noise and to provide the transient current to maintain a stable input and output voltage. a 10 f ceramic capacitor rated at 10 v is the minimum recommended value. increasing the capacitance reduces the switching ripple that couples into the power supply but increases the capacitor size. because the current at the inpu t terminal of the pwm amplifier is discontinuous, a capacitor with low effective series inductance ( esl ) is preferred to reduce voltage spikes. in most applications, a decoupling capacitor is used in parallel with the input capacitor. the decoupling capac itor is usually a 100 nf ceramic capacitor with very low esr and esl, which provides better noise rejection at high frequency band s. p ower d issipation this section provides guidelines to calculate the power dissipation of the ADN8834 . approximate t he total power dissipation in t he device by p loss = p pwm + p linear where: p loss is the total power dissipation in the ADN8834 . p linear is the power dissipation in t he linear regulator . pwm regulator power dissipation the pwm power stage is configured as a buck regulator and its dominant power dissipation (p pwm ) includes power switch conduction losses (p cond ), switching losses (p sw ), and transition losses (p tran ). other sources of power dissipation are usually less significant at the high output currents of the application thermal limit and can be neglected in approximation . use t he following equation to estimat e the power dissipation of the buck regulator : p loss = p cond + p sw + p tran conduction loss (p cond ) the conduction loss consists of two parts: inductor conduction loss (p cond_l ) and power switch conduction loss (p cond_s ). p cond = p cond_l + p cond_s inductor conduction loss is proportional to the dcr of the output inductor , l. using a n inductor with low dcr enhance s the overal l efficiency performance. e stimat e inductor conduction loss by p cond _l = dcr i out 2 power switch conduction losses are caused by the flow of the output current through both the high - side and low - side power switches, each of which has its own internal on resistance (r dson ). use the following equation to estimate t he amount of power switch conduction loss: p cond _s = ( r dson_hs d + r dson_ls (1 ? d )) i out 2 where: r dson_hs is the on resistance of the high - side mosfet. d is the duty cycle ( d = v out / v in ). r dson_ls is the on resistance of the low - side mosfet. rev. a | page 21 of 27
ADN8834 data sheet s witch ing l oss (p sw ) s witching losses are associated with the current drawn by the controller to turn the power devices on and off at the switching frequency. each time a power device gate is turned on or off, the controller transfers a charge from the input supply to the gate, and then from the gate to ground. use the following equation to estimate the switching loss: p sw = (c gate _hs + c gate _l s ) v in 2 f sw w here: c gate _hs is the gate capacitance of the high - side mosfet. c gate _l s is the gate capacitance of the low - side mosfet. f sw is the switching frequency . for the ADN8834 , t he total of ( c gate_hs + c gate_ls ) is approximately 1 n f. transition l oss (p tran ) transition losses occur because the high - side mosfet cannot tu rn on or off instantaneously. during a switch node transition, the mosfet provides all the inductor current. the source - to - drain voltage of the mosfet is half the input voltage, resulting in power loss. transition losses increase with both load and input voltage and occur twice for each switching cycle. use the following equation to estimate the transition loss: p tran = 0.5 v in i out ( t r + t f ) f sw where: t r is the rise time of the switch node. t f is the fall time of the switch node. for the ADN8834 , t r and t f a re both approximately 1 ns. linear regulator power dissipation the power dissipation of the linear regulator is given b y the following equation : p linear = [( v in ? v out ) i out ] + ( v in i gnd ) w here: v in and v out are the input and output voltages of the linear regulator. i out is the load current of the linear regulator. i gnd is the ground current of the linear regula tor. power dissipation due to the ground current is generally small and can be ignored for the purposes of this calculation . rev. a | page 22 of 27
data sheet ADN8834 rev. a | page 23 of 27 pcb layout guidelines temperature signal conditioning tec voltage limiting tec current limiting tec voltage sensing tec current sensing tec driver object thermoelectric cooler (tec) temperature error compensation temperature sensor source of electrical power target temperature 12954-033 figure 40. system block diagram block diagrams and signal flow the ADN8834 integrates analog signal conditioning blocks, a load protection block, and a tec controller power stage all in a single ic. to achieve the best possible circuit performance, attention must be paid to keep noise of the power stage from contaminating the sensitive analog conditioning and protection circuits. in addition, the layout of the power stage must be performed such that the ir losses are minimized to obtain the best possible electrical efficiency. the system block diagram of the ADN8834 is shown in figure 40. guidelines for reducing noise and minimizing power loss each printed circuit board (pcb) layout is unique because of the physical constraints defined by the mechanical aspects of a given design. in addition, several other circuits work in conjunction with the tec controller; these circuits have their own layout requirements, so there are always compromises that must be made for a given system. however, to minimize noise and keep power losses to a minimum during the pcb layout process, observe the following guidelines. general pcb layout guidelines switching noise can interfere with other signals in the system; therefore, the switching signal traces must be placed away from the power stage to minimize the effect. if possible, place the ground plate between the small signal layer and power stage layer as a shield. supply voltage drop on traces is also an important consideration because it determines the voltage headroom of the tec controller at high currents. for example, if the supply voltage from the front- end system is 3.3 v, and the voltage drop on the traces is 0.5 v, pvin sees only 2.8 v, which limits the maximum voltage of the linear regulator as well as the maximum voltage across the tec. to mitigate the voltage waste on traces and impedance interconnec- tion, place the ADN8834 and the input decoupling components close to the supply voltage terminal. this placement not only improves the system efficiency but also provides better regulation performance at the output. to prevent noise signal from circulating through ground plates, reference all of the sensitive analog signals to agnd and connect agnd to pgnds using only a single point connection. this ensures that the switching currents of the power stage do not flow into the sensitive agnd node. pwm power stage layout guidelines the pwm power stage consists of a mosfet pair that forms a switch mode output that switches current from pvin to the load via an lc filter. the ripple voltage on the pvin pin is caused by the discontinuous current switched by the pwm side mosfets. this rapid switching causes voltage ripple to form at the pvin input, which must be filtered using a bypass capacitor. place a 10 f capacitor as close as possible to the pvin pin to connect pvin to pgnds. because the 10 f capacitor is sometimes bulky and has higher esr and esl, a 100 nf decoupling capacitor is usually used in parallel with it, placed between pvin and pgnds. because the decoupling is part of the pulsating current loop, which carries high di/dt signals, the traces must be short and wide to minimize the parasitic inductance. as a result, this capacitor is usually placed on the same side of the board as the ADN8834 to ensure short connections. if the layout requires that a 10 f capacitor be on the opposite side of the pcb, use multiple vias to reduce via impedance. the layout around the sw node is also critical because it switches between pvin and ground rapidly, which makes this node a strong emi source. keep the copper area that connects the sw node to the inductor small to minimize parasitic capacitance between the sw node and other signal traces. this helps minimize noise on the sw node due to excessive charge injection. however, in high current applications, the copper area may be increased reasonably to provide heat sink and to sustain high current flow. connect the ground side of the capacitor in the lc filter as close as possible to pgnds to minimize the esl in the return path.
ADN8834 data sheet linear power stage layout guidelines the l inear power stage consists of a mosfet pair that forms a l inear amplifier, which operates in linear mode for very low output currents, and changes to fully enhanced mode for greater output currents. because the linear power stage does not switch currents rapidly like the pwm power stage , it does not generate noise currents . h owever , the linear power stage still requires a minim um amount of bypass capacitance to decouple its input. place a 100 nf capacitor that connects from pvin to pgndl as close as possible to the pvin pin . placing the thermistor amplifier and pid components the thermistor conditioning and pid compensation amplifiers work with very small signals and have gain ; therefore , attention must be paid when placing the external components with these circuits. place the thermistor conditioning and pid circuit components close to each other near the inputs of chopper 1 and chopper 2. avoid crossing paths between the amplifier circuits and the power stages to prevent noise pickup on the sensitive nodes. always reference the thermistor to agnd to have the cleanest connection to the amplifier input and to avoid any noise o r offset build up. e xample pcb l ayout u sing t wo l ayers figure 41, figur e 42 , and fi gure 43 show an example ADN8834 pcb layout tha t us es two layers. this layout example achieves a small solution size of approximately 20 mm 2 with all of the c onditioning circuitry and pid included. using more layers and blind s via allow s the solution size to be reduced even further because more of the discrete components can relocate to the bottom side of the pcb . r bp 0201 c vdd 0201 c bulk 0402 0201 0201 c itec vtec pgnd tempset vin tec + tec ? ntc connect to ground plane connect to ground plane units = (mm) c bu 04 u ulk 402 u 0 u 4 u l 0805 c sw_out 0402 c in _ s c in _ l r bp 0201 20 r b 02 201 0201 201 bp b bp b r c2 0201 c vdd vdd 0201 02 20 bp b r c1 0201 r v2 0201 r v1 0201 r b 0201 r a 0201 r 0201 r x 0201 c vref 0201 c i 0402 c f 0201 c d 0201 r d 0201 r i 0201 r p 0201 r fb 0201 c l_out 0201 c vdd r bp pgndl pgndl out 1 in 1 p in 2 p ldr ldr in 1 n in 2 n vlim / sd pvin pvin itec out 2 ilim sw sw vtec en / sy vdd pgnds pgnds sfb agnd vref c in _ s c in _ l c vdd p ndl pgndl pnl pgndl out ut 1 in n 1 1 p in n 2 2 p 0 02 02 02 0 02 0 20 0 20 2 01 1 1 01 01 l 20 20 0 0 l 20 l r 20 20 r 2 2 l l ld ld l l dr dr r dr n in 1 1 1 n in n n 2 2 2 2 n vlim im / sd sd vi pvin vi vi pvin ec tec itec out out ut ut 2 2 ilim lim 0 0 0 0 2 02 2 2 02 02 01 01 0 01 0 1 1 1 s 20 20 2 2 20 20 w 20 20 s 0 0 w 0 0 w 0 0 s s s s sw s s sw sw w sw v v te te vtec en n / / sy sy dd vdd d vd p p p p pn pgn n n n n gn nds nds s ds s p gn p g s nds n s s p p p p p pg n gn gn nd nds ds s s p pgn p nds n s s s p sfb sfb agnd gn ef v vr re re connect agnd t o pgnds on l y a t a single point as a s t ar connection agnd 4.0 3.5 3.0 2.5 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.0 12954-034 figure 41 . e xample pcb l ayout u sing t wo l ayers (top and bottom layers) rev. a | page 24 of 27
data sheet ADN8834 figur e 42 . e xample pcb l ayo ut u sing t wo l ayers (top layer o nly) rev. a | page 25 of 27
ADN8834 data sheet r bp 0201 c vdd 0201 vdd 201 r bp c bulk 0402 ul 0 0201 0201 itec vtec pgnd tempset vin tec+ tec? ntc 4.0 3.5 3.0 2.5 1.5 1.0 0.5 0 connect to ground plane connect to ground plane units = (mm) c in_s c in_l 0 c vdd r bp agnd 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.0 12954-036 fi gure 43 . e xample pcb l ayo ut u sing t wo l ayers (bottom layer o nly) rev. a | page 26 of 27
data sheet ADN8834 outline dimensions 06-07-2013- a pkg-003121 a b c d e 0.660 0.600 0.540 2.58 2.54 sq 2.50 1 2 3 4 5 bot t om view (bal l side up) t op view (bal l side down) end view 0.360 0.320 0.280 bal l a1 identifier sea ting plane 0.390 0.360 0.330 coplanarity 0.05 2.00 ref 0.50 bsc 0.270 0.240 0.210 figure 44 . 25- ball wafer level chip scale package [wlcsp] (cb - 25- 7) dimensions shown in millimeters 0.50 bsc 0.50 0.40 0.30 compliant to jedec standards mo-220-wggd-8. bot t om view t o p view 4.10 4.00 sq 3.90 se a ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 pin 1 indic a t or 1 24 7 12 13 18 19 6 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 12-03-2013- a 0.30 0.25 0.18 pin 1 indic a t or 0.20 min 2.70 2.60 sq 2.50 exposed pad pkg-004273 figure 45 . 24 - lead lead - frame chip scale package [lfcsp _wq ] (cp - 24 - 15 ) dimensions shown in millimeters ordering guide model 1 temperature range 2 package description package option ADN8834acbz - r7 ?40c to +125c 25- ball wafer level chip scale package [wlcsp] cb -25-7 ADN8834c b - evalz 25- ball wlcsp evaluation board: 1.5 a tec c urrent l imit, 3 v tec v oltage l imit ADN8834acpz - r2 ?40c to +125c 24- lead lead fr ame chip scale package [lfcsp_wq ] cp -24-15 adn 8834ac p z - r7 ?40c to +125c 24- lead lead fr ame chip scale package [lfcsp _wq ] cp -24-15 adn8 834cp - evalz 24- lead lfcsp evaluation board : 1.5 a tec current l imit, 3 v tec v oltage l imit ADN8834mb - evalz mother evaluation board of the ADN8834 for pid tuning 1 z = rohs compliant part. 2 operating junction temperature range. the ambient operating temperature range is ?40c to +85c . ? 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d12954 - 0 - 8/15(a) rev. a | page 27 of 27

▲Up To Search▲

Price & Availability of ADN8834

	To Download ADN8834 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .